Analyst

Should have at least 8 years of experience in RTL design/integration, synthesis and static timing analysis

Should have a good knowledge of industry leading synthesis and STA tools. Should have prior working experience at both IP and full-chip levels and should have supported in tape-out activities

Should have experience in pre-layout and post-layout timing analysis and should have experience in working closely with physical design teams to achieve timing closure

Should have good scripting abilities (PERL/TCL) and should have experience in setting up synthesis and STA flows from scratch