Senior Engineer Verification

Responsible for developing and maintaining testbenches, debugging and optimizing Verification IP, and applying advanced verification methodologies such as UVM with System Verilog. Perform functional verification of IP modules in VHDL or Verilog and continuously enhance verification strategies to improve coverage, efficiency, and reliability

Your Role

Key responsibilities in your new role

• Assist in the development of testbenches
• Debug and optimize verification IP
• Apply methods like UVM with System Verilog
• Perform verification of IP modules (VHDL or Verilog)
• Enhance the pool of our verification methods
  
  

Your Profile

Qualifications And Skills To Help You Succeed

• B.E./B.Tech/M.E./M.Tech in Electrical /Electronics/ Computer science
• Bachelor's - 2 to 4 years’ experience, Master’s - 1 to 2 years experience
• Looking for the candidates who
• Have very good knowledge of an HDL such as VHDL or Verilog
• Have good programming skills, e.g. in C, Python or Perl, as well as good Linux skills
• System Verilog knowledge is a plus
  
  

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