Senior Memory Design Engineer

Broadcom


Date: 4 hours ago
City: Bengaluru, Karnataka
Contract type: Full time
Job Description:

JD for Senior Design Engineer


  • Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies
  • Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
  • Development of critical path and characterization flow to perform detailed margin and characterization simulations.
  • Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
  • Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
  • Logic simulations and detailed timing analysis of key paths in high speed memory design.
  • Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.


Skill Sets/Prerequisites


  • Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
  • Experience in Designing and driving one or many Memory Compilers Specifications to final release
  • Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
  • Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.


5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools


  • Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
  • Experience in Skill/Perl/Python Scripting is a strong plus
  • Experience in Understanding the layout design issues in sub nanometer regime is a must.
  • Expertise in Understanding Memory DFT is a Plus.
  • Masters Degree with 4+ Years or Bachelors Degree with 5+ years


R027062

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