Physical Design - Flip Chip Lead (Bump, TSV, RDL)

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Description

Sr. Staff Engineer, Physical Design – Full Chip Lead (SoC Integration, Bump, TSV, RDL)

Function: ASIC Design / Physical Design | Location: [Bangalore]

Role Summary

Own full-chip physical design for advanced-node SoCs, from floorplan and integration through timing, power and physical convergence to tape-out. You will lead the chip-level implementation across blocks and partitions, including package-aware bump, RDL and TSV planning. You will work with Architecture, RTL, DFT, STA/Signoff, Package, SI/PI, IP and Foundry teams.

Key Responsibilities

• Full-chip integration: Own chip-level floorplan, partitioning, top-level assembly, clocking, power grid and block-level hand-offs. Drive hierarchical and flat implementation strategy.
• Convergence: Lead timing, power, area, congestion and DRC closure across partitions and corners. Manage ECOs through final signoff.
• Bump, RDL and TSV: Define the bump map and RDL stack-up and routing. Plan TSV placement for multi-die and 2.5D/3D designs. Co-optimize with the package for power, signal integrity and manufacturability.
• Power integrity and reliability: Close chip-level IR drop and EM with the PI team. Cover power-grid, bump and package interaction.
• Signoff and tape-out: Own physical verification (DRC, LVS, antenna, density), STA and power signoff, and a clean tape-out hand-off.
• Flow and methodology: Define and automate the full-chip flow, set best practices, and evaluate new tools and techniques.
• Leadership: Lead and mentor engineers, set technical direction, and manage schedule and risk. Interface with Foundry, OSAT and EDA vendors, and report status to program and management teams.
  
  

Qualifications

• BS/MS in Electrical Engineering or a related field.
• 10+ years in ASIC physical design, including several full-chip tape-outs at advanced nodes (7nm and below preferred).
• Strong experience in chip-level floorplanning, integration and timing/power convergence.
• Hands-on bump and RDL experience. Knowledge of package technologies (FCBGA, interposer, microbump/C4) and IR/EM analysis.
• Tools: Innovus or ICC2/Fusion Compiler, PrimeTime, Calibre, and RedHawk or Totem.
• Scripting in Tcl, Python or Perl.
• Preferred: TSV, 2.5D/3D or multi-die experience, die-to-die interfaces such as UCIe, and low-power (UPF) and multi-voltage design.
  
  

Additional Information

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.